In the development of complementary MOS (CMOS) devices, there has been a continual effort to fit more devices into a given area of a semiconductor wafer. FIGS. 1–5 illustrate several stages of that development.
FIG. 1A illustrates a standard CMOS structure that would normally be used in devices having a feature size of 1.2 μm or larger. CMOS 10 includes a P-channel MOSFET 10a and an N-channel MOSFET 10b and is formed in a P substrate 11. Typically, many other NMOSFETs and PMOSFETs would be formed in P substrate 11. P-channel MOSFET 10a is formed in an N-well 14, which is formed by a conventional implant and extended diffusion process. Thus N-well 14 is implanted into a relatively shallow depth of substrate 11 and expands both vertically and horizontally when exposed to a thermal process.
MOSFETs 10a and 10b are both lateral devices and include gates 12a, 12b, respectively, that are separated from the substrate 11 by a gate oxide layer 16. PMOSFET 10a includes a P+ source region 13a, a P+ drain region 13b and an N+ contact region 13c, which is used to make contact with N-well 14. NMOSFET 10b includes an N+ source region 14a, an N+ drain region 14b and a P+ contact region 14c, which is used to make contact with P substrate 11, which is the body of NMOSFET 10b, via a metal contact 18. The channel regions under the gates 12a, 12b may or may not contain a threshold adjustment implant.
Metal contact 18 is tied to the most negative voltage in the system, which is normally ground. Therefore, CMOS 10 cannot operate at voltages very far above ground. Moreover, NMOSFET 10b shares a common body terminal with any other NMOSFET in CMOS 10, and any currents or noise that are injected into substrate 11 are coupled to NMOSFET 10b and any other NMOSFETs in the device, since the NMOSFETs are not isolated.
In CMOS 10, the doping concentration of substrate 11 must be designed to set the electrical characteristics of NMOSFET 10b. This limitation is ameliorated in CMOS 20, shown in FIG. 1B, where NMOSFET 10b is formed in a P-well 21. The main purpose of forming NMOSFET 10b in P-well 21, however, is to control the breakdown and punchthrough characteristics of NMOSFET 10b. Since there is no PN junction between P substrate 11 and P-well 21, NMOSFET 10b still shares the same body with any other NMOSFET in CMOS 20 and any other substrate-connected device, since the body terminal of NMOSFET 10b is electrically common with P-substrate 11 and since N+ regions 14a and 14b cannot be biased to large voltages above the potential of P-substrate 11.
FIG. 1C illustrates in general a process that can be used to fabricate CMOS 20. The process starts with the formation of a field oxide layer on P substrate 11. The substrate is masked, and N-well 14 is formed by an implant and diffusion of phosphorus. The substrate is again masked, and P-well 21 is formed by an implant and diffusion of boron.
Next, there are two variations of the process. In one, the active device areas are defined by a mask and the field oxide layer is etched from the active device areas. In the other, the field oxide layer is stripped and a pad oxide layer is thermally grown. Field oxide regions are formed by a conventional LOCOS process, which includes defining the active device areas by patterning a nitride layer and etching the nitride layer from the areas where field oxide is to be grown. A blanket phosphor implant is performed to form an N field deposition (NFD), and a mask is formed to define areas where boron will be implanted to form a P-field deposition (PFD). The field oxide regions are then formed in areas where the nitride layer has been removed, the nitride layer is stripped, and a sacrificial oxide layer is grown and stripped to repair crystal damage and remove any silicon nitride residues that might impair the proper growth of the gate oxide.
A gate oxide layer is then deposited, and a polysilicon layer is deposited, doped, masked and etched to form the gates of the MOSFETs. The source and drain regions of PMOSFET 10a are formed by masking the substrate and implanting boron, and the source and drain regions of NMOSFET 10b are formed by masking the substrate and implanting phosphorus and/or arsenic. An anneal is applied to drive in the boron and phosphorus/arsenic implants.
A conventional interconnect formation process is then performed, including the deposition and etching of glass layers and the deposition (sputtering) of metal layers that contact the source, drain and body regions of PMOSFET 10a and NMOSFET 10b. 
FIG. 2A shows a CMOS 30 that is produced using a more modern process that is capable of fabricating devices with a smaller gate dimension. N-well 14 contains a PMOSFET 30a and P-well 21 contains an NMOSFET 21. N-well 14 and P-well 21 are formed as complements of each other, i.e. the entire surface of substrate 11 is occupied by either an N-well 14 or a P-well 21. An oxide sidewall spacer 19 is formed on gates 12a, 12b. Oxide sidewall spacer inhibits the implanting of high-concentration dopant into substrate 11 thereby forming lightly-doped P− regions 33a, 33b adjacent the source and drain regions 13a, 13b in PMOSFET 30a and lightly-doped N− regions adjacent the source and drain regions 14a, 14b in NMOSFET 30b. A silicide layer 32 is formed on top of gates 12a, 12b. CMOS 30 is a non-isolated, twin well CMOS that represents the majority of CMOS devices in the 0.25 μm to 1.2 μm range. Like NMOSFET 10b shown in FIG. 1B, NMOSFET 30b shares a common body region with all other NMOSFETs in CMOS 30. Therefore, NMOSFET 30b must be biased near ground and is sensitive to any noise that may appear in P substrate 11.
CMOS 40, shown in FIG. 2B, is similar to CMOS 30 but is formed in a lightly-doped P− epitaxial (epi) layer 41 that is in turn grown on a heavily-doped P+ substrate 42. This is generally done to improve the latch-up characteristics of the device by preventing lateral voltage drops along the substrate. Heavily-doped P+ substrate 40 has a lower resistivity that the P− substrate 11 shown in FIG. 2A. This is an indication of the problems that can occur in non-isolated devices that share a lightly-doped common body region. While the heavily-doped substrate can reduce latch-up in a normal digital IC, it does not offer sufficient protection against latch-up in power and high-current ICs.
“Epitaxial” refers to the growth of a single-crystal semiconductor film on a single-crystal substrate of the same semiconductor. The word “epitaxial” is derived from the Greek meaning “arranged upon”. See, A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons (1967), pp 7–20.
FIG. 2C illustrates a process that can be used to fabricate CMOS devices 30 and 40. In the case of CMOS 30 the process starts with P− substrate 11; in the case of CMOS 40 the process starts with P+ substrate 42 and includes growing P− epi layer 41 on top of P+ substrate 42. The complementary well formation and LOCOS field oxide formation are substantially the same as the processes described in FIG. 1C. The gate formation includes the formation of a metal layer by chemical vapor deposition on top of the polysilicon gate, followed by a silicidation process.
Following the gate formation, the substrate is masked and phosphorus is implanted to form lightly-doped N− regions 34a, 34b. The mask is removed and another mask is formed to define the lightly-doped P− regions 33a, 33b. BF2 is implanted to form P− region 33a, 33b. The sidewall oxide or glass is then deposited and etched to form sidewall spacers 38a, 38b, 39a and 39b. 
The substrate is masked and arsenic is implanted to form N+ regions 14a, 14b. The substrate is masked again and BF2 is implanted to form regions 13a, 13b. An anneal is performed to drive in the dopants.
The interconnect formation includes the deposition of two Al—Cu layers with intervening dielectric layers. A rapid thermal anneal (RTA) is performed, a glass layer is deposited, patterned and etched, and a Ti or TiN adhesion layer is deposited on the glass before the first Al—Cu layer. Typically, the glass layer such as spin-on glass or BPSG is planarized by etchback or chemical-mechanical polishing (CMP) prior to patterning. The deposition of the second glass layer is followed by a via mask and etch, a tungsten deposition and etchback and the deposition of the second Al—Cu layer. The second glass layer, which may be a chemical vapor deposition (CVD) layer with TEOS as a precursor or a spin-on glass (SOG) layer, should be formed at a low temperature to avoid melting the first metal layer. The tungsten plug is typically used to planarize the via hole prior to the deposition of the second metal layer. The planarization is carried out by etchback or CMP.
FIG. 3A illustrates a substantially different approach to the fabrication of a CMOS device, using technology that evolved from the fabrication of bipolar devices. CMOS 50 includes an NMOSFET 50a, formed in a P-well 56, and a PMOSFET 50b, formed in an N-well 55. P-well 56 and N-well 55 are formed in an N− epi layer 52 that is grown over a P substrate 51. NMOSFET 50a includes an N+ source region 60a and an N+ drain region 60b. Lightly-doped N regions 62a, 62b are formed adjacent to regions 60a, 60b, respectively. A gate is formed over a gate oxide layer 65, and a silicide layer 59 is deposited on the gate. Contact to P-well 56 is made via a P+ region 61c. 
PMOSFET 50b includes a P+ source region 61b and a P+drain region 61a. Lightly-doped P regions 63a, 63b are formed adjacent to regions 61a, 61b, respectively. A gate is formed over gate oxide layer 65, and silicide layer 59 is deposited on the gate. Contact to N-well 55 is made via an N+ region 60c. 
Regions of N− epi layer 52 are isolated from each other by stacks of P diffusions, such as the stack containing a P buried layer 53 and P-well 56, which are implanted at the top and bottom of N− epi layer 52 and then heated so as to cause them to diffuse upward and downward until they merge. The “thermal budget” (i.e., the product of temperature and time) that is necessary to cause P buried layer 53 and P-well 56 to diffuse in this way is substantial and ends up setting many of the electrical characteristics of the arrangement. Moreover, P buried layer 53 and P-well 56 also diffuse in a lateral direction, and this limits the packing density of the devices.
FIG. 3B illustrates a variation in which N buried layer 54 has been replaced by a hybrid N buried layer 71 in a CMOS device 70. N buried layer 71 is generally doped with phosphorus but contains a central region 72 that is doped with antimony. The phosphorus-doped portion of N buried layer 71 has diffused upward to merge with N-well 55, eliminating the intervening segment of N-epi layer 52 that is shown in CMOS device 50 of FIG. 3A. This provides a low-resistance path to N-well 55 and helps to prevent latch-up resulting from lateral voltage drops in N-well 55. Nonetheless, P-well 56 is still electrically tied to P-substrate 51, creating the limitations and problems described above.
FIGS. 3C–3E are graphs of doping concentration versus depth into the substrate at the cross sections indicated in FIGS. 3A and 3B. As these graphs suggest, the processes required to form these CMOS devices are highly susceptible to variations in such parameters as epitaxial thickness, diffusivity and temperature, and in addition they tend to be quite expensive, requiring long processing times and dedicated high-temperature diffusion furnaces. The process shown, moreover, requires the P-type buried layer, the arsenic N-type buried layer and the phosphorus N-type buried layer each to have its own dedicated mask, making the process even more expensive.
FIG. 4A is a schematic circuit diagram of CMOS devices 50a and 50b, shown in FIGS. 3A and 3B, respectively. Substrate 51 is shown as ground. PMOSFET 50b is shown as isolated from ground by diode 97, which represents the PN junction between P− substrate 51 and N buried layer 71. Diodes 95 and 96 represent the junctions between P+ source region 61b and P+ drain region 61a, respectively, and N well 55. NMOSFET 50a is shown as non-isolated. Diodes 92 and 93 represent the junctions between N+ drain region 60b and N+ source region 60a, respectively, and P well 56.
FIG. 4B illustrates a PNP bipolar transistor that can also be formed from this process. P+ region could be the emitter, N well 55 and N buried layer 71 could be the base, and P substrate 51 could be the collector.
FIG. 5A shows a CMOS device 100 that contains three buried layers: an N buried layer 103 (NBL2) of phosphorus underlying N well 104, a P buried layer 106 underlying P well 105, and an N buried layer 102 (NBL1) of antimony (or arsenic) that extends continuously under N well 104 and P well 105. PMOSFET 100a and NMOSFET 100b are similar to PMOSFET 50a and NMOSFET 50b shown in FIGS. 3A and 3B.
Extending N buried layer 102 under P well 105 has the effect of isolating PMOSFET 100a from the P-substrate 101. Thus all of the MOSFETs are isolated from the substrate. Adding N buried layer 102 requires an additional mask, however, and the diffusion of N buried layer 102 during the long isolation diffusion adds still more variability to the process. Therefore, it is necessary to overdesign all parameters including all updiffusion of buried layers, epi layer 114 may have to be grown to a thickness over 6 μm just to form 30V devices (that ideally less than 2 μm of silicon could support). In addition, the lateral diffusion of all the buried layers and the updiffusion of N buried layer 102 that occurs during the isolation (well) drive-ins further reduces the packing density that can be achieved.
FIG. 5B illustrates a possible process sequence for CMOS device 100. The process starts with a P substrate on which a thick oxide layer is formed. A mask is formed for N buried layer 102 and antimony and phosphorus are implanted and allowed to diffuse by thermal processing.
Then a choice is made between a complementary buried layer process and a multiple buried layer process. In the multiple buried layer process, separate masks are used to define the locations of N buried layer 103 and P buried layer 106, respectively. Each masking step is followed by an implant of either N-type dopant (phosphorus) or P-type dopant (boron) and after the implant the dopants are diffused by thermal processing. In the complementary buried layer process, a nitride layer is deposited and then patterned and etched by using the CBL mask, followed by the implantation of one of the two wells, which is subsequently oxidized. The nitride prevents the oxidation in the regions not receiving the first well implant, while the first well becomes covered by a thick oxide. The nitride is then stripped and the second well implant, the complement to the first, is executed. The thick oxide blocks the implant from the first well region. The second well is then diffused and all of the oxide is stripped. Hence, one mask defines complementary wells.
After the three buried layers have been formed, a P− epitaxial layer is grown and the NMOS and PMOS devices are formed in the epitaxial layer as described above. As will be apparent, this is a very complicated process involving numerous masking steps. It is possible, for example, to spend $150 just on the formation of the buried layers in a 6-inch wafer. If a mistake is then made in the fabrication of the NMOSFETs or PMOSFETs, that cost is entirely lost. Moreover, the multiple diffusions that are necessary create numerous possibilities for error, and even if the diffusions are carried out perfectly, the lateral diffusion of dopant that is inherent in the process reduces the number of devices that can be formed in a given area of substrate.
FIG. 5C shows a dopant profile taken at cross-section 5C—5C in FIG. 5A. This shows a region of the P-epitaxial layer between the N buried layer 102 and the P well 105. In some cases N buried layer 102 merges with P well 105. This variability occurs mainly because P well 105 is referenced to the top surface of the epi layer while N buried layer 102 is referenced to the surface of P substrate 101. These variations can have a significant effect on the electrical characteristics of a device, including junction breakdown, resistance, capacitance, speed and current.
The schematic diagram of FIG. 5D shows the advantage of CMOS device 100. NMOSFET 100a has a body that is tied to a separate terminal 110a and can be biased independently of the P substrate 101. Diode 127, which represents the PN junction between P well 105 and N buried layer 102, and diode 128, which represents the PN junction between N buried layer 102 and P substrate 101, provide isolation for NMOSFET 100a. The cathodes of diodes 127 and 128 are N buried layer 102.
FIGS. 5A–5D demonstrate that to form an isolated structure a very complicated, costly process is required, with numerous sources of variability and possible error. This process is suited primarily to devices having large feature sizes and large lateral spacing and can be carried out only in manufacturing plants capable of high temperature operations. This process is inconsistent with the modern CMOS processes, such as the process shown in FIG. 2A, which represents roughly 90% of the manufacturing capacity currently in existence. Thus there is a basic inconsistency between the processes required to produce isolated CMOS devices and the manufacturing facilities available to produce such devices today. There is a definite need in the art of semiconductor manufacturing for a process that will overcome this problem.